Mixed-Signal IC Design · Complex PCB Design · FPGA · Embedded Firmware · C++ · Control Systems
Rajinthan Rameshkumar
Final Year · University of Moratuwa · NS-SAR ADC (SKY130)
I love working on mixed-signal IC design, especially low-power, high-speed data converters.
My work covers schematic design, custom test benches, simulation, layout, and three tapeout
submissions. I am a final-year Electronic & Telecommunication Engineering undergraduate at
the University of Moratuwa, currently working on a low-power noise-shaping SAR ADC in SKY130.
I also design complex embedded PCBs, including six-layer GaN motor-controller boards. I have
a paper accepted at SMACD 2026 and placed 3rd globally at the International Microelectronics
Olympiad.
A 2.4 GHz LC-VCO Fractional-N Phase Locked Loop Open-Source Design in 130 nm BiCMOS
M. Thiriloganathan, S. Ranasinghe, A. Herath,
R. Rameshkumar, H. Marasinghe, A. Viduranga,
G. Leelarathne, K. Wickremasinghe
SMACD 2026, International Conference on Synthesis, Modelling, Analysis and
Simulation Methods and Applications to Circuit Design, 2026.
Preprint: arXiv:2607.08852.
University of Moratuwa, Sri Lanka · Aalto University, Finland · University of British Columbia, Canada
My contribution was the PFD and charge pump design. I iterated both blocks with custom
xschem test benches, then used Magic for PCell generation and parasitic extraction, and
KLayout for placement and routing. The team developed the PLL in the IHP SG13G2 130 nm
BiCMOS PDK under the IEEE CASS UNIC-CASS programme.
Two- and six-layer boards from schematic capture and component selection through PCB layout and manufacturing handoff. Work includes GaN motor drives, sensor interfaces, power management, and NFC reader circuits.
Altium Designer
KiCad · EasyEDA
Motor Drive
Power Management
PCB Layout
6-Layer Boards
Fabrication Handoff
◔
Analog IC Design
CMOS circuit design using open-source and commercial PDKs, including op-amps, PLLs, VCOs, charge pumps, PFDs, and SAR ADCs. Full flow from schematic and simulation to layout verification.
CMOS Amplifiers
PLL / VCO / PFD
NS-SAR ADC
SKY130A
IHP SG13G2
Cadence Virtuoso · xschem
☰
FPGA & Digital Design
RTL design in Verilog targeting Intel/Altera FPGAs. Custom IP blocks (UART, cache architectures), FSM design, arithmetic pipelines, and hardware simulation in ModelSim.
Verilog
Intel Quartus
Altera DE0-Nano
Cache Design
UART / FSM
ModelSim
❖
Firmware Engineering
Register-level and HAL-based C/C++ firmware on STM32 (F4, H7) and ESP32. Peripheral integration (SPI, UART, I2C, CAN, DMA), display drivers, real-time PID control, and encoder feedback loops.
STM32F4 / F405
ESP32
C / C++
FOC / PID Control
SPI / UART / DMA
STM32CubeIDE
◐
Mixed-Signal IC & Layout
Custom IC layout for analog and mixed-signal blocks, including floor-planning, DRC/LVS verification, parasitic extraction, and post-layout simulation. Tapeout submission experience on both SKY130A and IHP SG13G2 PDKs.
KLayout
Magic
DRC / LVS
Parasitic Extraction
Tiny Tapeout
UNIC-CASS
Post-Layout Sim
↻
Control Systems & DSP
PID, FOC (Field-Oriented Control), encoder-based speed/acceleration loops, and signal processing algorithms deployed in real-time on embedded hardware. MATLAB/Simulink for model-based design.
PID Tuning
FOC Algorithms
Encoder Feedback
MATLAB / Simulink
Signal Filtering
ADCS / Reaction Wheels
Selected Work
8-bit SAR Core · Tiny Tapeout
Analog IC · Final Year Project · Tiny TapeoutJan 2026 to Present
Low-Power Noise-Shaping SAR ADC in SKY130 CMOS
Final year project: Low-Power Noise-Shaping SAR-ADC in SKY130 CMOS Process for
Energy Constrained Sensing Applications. Our team has submitted the 8-bit
differential SAR ADC core to Tiny Tapeout on SKY130. This is an intermediate step
towards the full noise-shaping ADC. I am working on the comparator, exploring dynamic
amplifiers to reduce power, and on capacitor-and-switch noise-shaping filters. I use
Cadence Virtuoso for schematic design, simulation, and layout. The noise-shaping loop
is still in development.
Submitted core 8-bit differential SAR ADC
PDK SKY130
Shuttle Tiny Tapeout SKY 26c
Status Core submitted
8-bit SAR CoreSKY130Tiny TapeoutNS-SAR FYP
Submission and project scope
The Tiny Tapeout submission contains the fully differential 8-bit SAR core, including
the capacitive DAC, comparator, and SAR control logic. The wider final year project
aims to add the noise-shaping loop in a later revision. My current work focuses on
the comparator and dynamic amplifier options for lower power, along with
capacitor-and-switch noise-shaping filters in Cadence Virtuoso. This submission
does not include the noise-shaping loop or measured silicon results.
Layout views
Submitted SAR core layoutThree-dimensional layout view8-bit SAR core
Analog IC · RF · IEEE CASS · SMACD 2026 ✓Aug 2025 to Present
2.4 GHz Fractional-N PLL with LC-VCO
Designing a 2.4 GHz Type-II ΔΣ Fractional-N Phase-Locked Loop coupled with a
Type-IV Cross-Coupled Differential LC Voltage-Controlled Oscillator for WiFi/Bluetooth
applications. Developed using the IHP SG13G2 PDK for the UNIC-CASS programme by IEEE CASS.
I designed and iterated the PFD and charge pump using custom xschem test benches.
For layout, I used Magic for PCell generation and parasitic extraction, and KLayout
for placement and routing.
Paper accepted at SMACD 2026. This was a team project
with eight co-authors across the University of Moratuwa, Aalto University, and UBC.
Preprint: arXiv:2607.08852.
Frequency 2.4 GHz
PDK IHP SG13G2
Type Frac-N ΔΣ
VCO Cross-coupled LC
PLLVCOIHP SG13G2IEEE CASSRFSMACD 2026
Architecture
A charge-pump Type-II PLL with fractional-N division using a ΔΣ modulator (DSM).
A 10 MHz crystal oscillator drives the Phase-Frequency Detector (PFD), which compares
the reference against the divided VCO output. The charge pump and passive loop filter
generate the VCO control voltage, while the DSM dithers the integer divider to achieve
fractional division ratios. This enables the output to lock anywhere in the 2.35 to 2.55 GHz
band with N ≈ 240 to 248. A bandgap reference provides supply-independent biasing.
Paper accepted at SMACD 2026 (International Conference on Synthesis,
Modelling, Analysis and Simulation Methods and Applications to Circuit Design) as part
of the IEEE CASS UNIC-CASS open-source IC design programme.
Single-Ended Two-Stage CMOS Op-Amp for Tiny Tapeout
Designed and submitted a single-ended (SE) two-stage CMOS operational amplifier
for Tiny Tapeout fabrication on the SKY130 PDK. Achieved a 2 nA disable current,
4 MHz unity-gain bandwidth, and 80 dB open-loop gain. Schematic and layout
developed in xschem, ngspice, and KLayout.
Open-loop Gain 80 dB
UGB 4 MHz
Disable Current 2 nA
PDK SKY130
SKY130Tiny TapeoutxschemKLayout
Architecture
The amplifier uses a common-source input stage with an active current-mirror load,
followed by a common-source second gain stage. A Miller compensation capacitor between
the two stages ensures stability. An on-chip bias network derives both the reference
and load currents from a single external Iref of 5 µA, making the design self-contained
for tapeout. An EN pin pulls the quiescent current down to 2 nA in disable mode.
Target Specifications
SupplyVDD = 1.8 V
Bias currentIref = 5 µA
Input common-mode≈ 0.9 V
Open-loop DC gain≥ 80 dB
Unity-gain bandwidth4 MHz
Phase margin≥ 60°
Disable current2 nA
LoadHigh-impedance (7 pF)
Schematic
Full schematic (xschem)Testbench setup
Simulation Results
AC gain responsePhase marginTransient responseSlew rate
Led design and development of an open-source 4WD micromouse robot at RoboticGen,
reaching 3 m/s (2× faster than the previous version). Custom STM32F405 PCB with
DRV8833 motor drivers reduced board size by 40%. PID motion control with quadrature
encoder and ICM-42688 IMU feedback for high-speed maze navigation.
MCU STM32F405 (Cortex-M4)
Max Speed 3 m/s
PCB reduction 40%
Control PID + encoder + IMU
STM32F405PCB DesignPIDC++
Overview
OBO Mouse v4 is an open-source four-wheel differential drive micromouse designed
for maze-solving competitions. The robot integrates closed-loop PID velocity control
with quadrature encoder feedback, a gyroscope/IMU for heading correction, and IR
sensors for wall detection. The chassis is lightweight and 3D-printable; the PCB
consolidates all electronics into a compact 2-layer board designed in EasyEDA.
Aerospace · PCB · Motor ControlDec 2025 to Jun 2026
Smart Reaction Wheel Controller for Satellite ADCS
Designed controller PCB revisions for a BLDC satellite reaction wheel at NUS StarLabs,
taking responsibility for the electronics, simulation, and R&D. I used Simulink to
simulate control firmware before implementing it on hardware. The boards integrate
motor drive, sensor feedback and communications, and were fabricated and assembled
through JLCPCB. I developed FOC and sensor-interfacing firmware for the
attitude-control application. The six-layer PCB uses a GaN-based drive stage designed
for 24 to 37 V and up to 10 A, with a 100 kHz control loop and 400 kHz switching.
Application Satellite ADCS
Control FOC · 100 kHz loop
PCB 6 layers · GaN drive
Drive rating 24 to 37 V · 10 A max
Altium6-Layer PCBGaN DriveFOC
Board development
The controller revisions bring together motor-drive circuitry, phase-current sensing,
feedback interfaces and communications for reaction wheel control. The images show PCB
layout, board renders, and a JLCPCB-assembled board.
Key Specifications
HardwareBLDC drive + sensor interfaces
ControlFOC
ApplicationSatellite ADCS
AssemblyJLCPCB
PCB6 layers
Control loop100 kHz
GaN switching400 kHz
Drive rating24 to 37 V · 10 A max
PCB Layout & Assembly
PCB layoutBoard renderAssembled board
BLDC Controller · PCB Prototype
Motor Control · PCB DesignJan 2026 to Apr 2026
BLDC Controller Prototype
Designed a PCB prototype for three-phase BLDC motor control, combining the controller,
motor-drive circuitry and feedback interfaces on a compact board. The board was assembled
through JLCPCB. Its six-layer design uses a GaN-based drive stage for 24 to 37 V and up to
10 A, with a 100 kHz control loop and 400 kHz switching.
Students tap an ID card on a pocket-sized logger built around an STM32L432 and an
ST25R3916 NFC reader. Each tap is stored in on-chip flash, and plugged into a PC the
unit appears as a USB drive of CSV files, with no driver needed. A desktop companion
app imports the taps, matches them to students and lectures, and exports reports.
Designed for low power: it idles at about 108 µA while waiting for cards and
draws 1.8 µA switched off, giving an estimated 17 months per charge.
MCU STM32L432
NFC ST25R3916, ISO 14443-A
USB FAT12 mass-storage drive
Power ~108 µA idle · 1.8 µA off
STM32NFCUSB MSCLow PowerKiCadPySide6
Firmware
Bare-metal C in two layers. All logic (card protocol, flash log, FAT12 volume,
settings parser, lecture sessions) is hardware-independent and runs on a PC under a
931-check host test suite; a thin HAL layer only hands up raw values.
Key Specifications
MCUSTM32L432KB · 4 MHz MSI
NFC readerST25R3916 · ISO 14443-A
USBFAT12 mass-storage drive
Log capacity6,858 taps in flash
Idle (waiting for cards)~108 µA
Switched off1.8 µA (measured)
Battery life (est.)~17 months · 1000 mAh
Companion appPySide6 + SQLite
Low-power design
Between taps the MCU sleeps in Stop 2, timed by LPTIM1 from the 32.768 kHz crystal,
and wakes only for a 10 ms heartbeat flash every 5 s. Meanwhile the ST25R3916
checks the antenna on its own every 100 ms in its wake-up mode and interrupts the
MCU only when a card detunes the field. The idle draw is about 108 µA, 91 %
of it the reader. The core runs at 4 MHz from MSI with the PLL off: a read is
bounded by the RF protocol, not computation, so a faster clock would only burn more
charge (at 4 MHz the MCU is 0.6 % of a read's charge). Switched off, the unit
sits in Standby at 1.8 µA, down from 4.8 µA once the reader's SPI pins
were pulled down; on battery it also switches itself off after 3 minutes without a tap.
Currents were measured on the board with a multimeter for steady loads and a
Tektronix TBS1052C across a 1 Ω shunt for the millisecond pulses (wake-up
checks, card reads, false wake-ups). A 100-student lecture costs about 0.36 mAh,
so at four lectures a day a 1000 mAh cell is estimated to last about 17 months,
including self-discharge.
Power report (PDF) →
Companion app
A PySide6 desktop app with an SQLite database: register students by tapping their
card, start lectures from the PC or the device's button, file each tap under its
lecture, and export attendance as CSV or PDF.
Board design
Two-layer KiCad board assembled by JLCPCB: USB-C with ESD protection, an MCP73833
Li-ion charger, a 3.3 V LDO, battery monitoring, LEDs and a vibration motor for
feedback. Antenna integration and tuning are the remaining hardware work.
Assembled NFC logger PCBPCB layout and antenna areaBoard render
Robotic end-effector using pneumatic actuation, vacuum suction cups, and an
ATmega2560 controller with register-level firmware for precise real-time control.
Time-of-Flight sensors enable angular alignment and adaptive handling of boxes
of varying sizes in warehouse depalletizing environments.
MCU ATmega2560
Gripping Vacuum + pneumatic
Alignment ToF sensors
PCB 2 layers · Altium
ATmega2560ToF SensorsRS485 / SPIAltiumSolidWorks
Overview
A reconfigurable robotic end effector designed for automated depalletizing in
supermarket warehouse logistics. The system combines vacuum suction cups for box
lifting, pneumatic cylinders for lateral stabilization, and ToF sensors for
real-time angular alignment. This enables the gripper to adapt to boxes of varying
sizes and weights without manual reconfiguration. The Altium-designed PCB
integrates RS485, UART, and SPI interfaces with solenoid switching and
flyback protection on a 2-layer board.
Four-way set-associative write-back cache in Verilog, 1 KB as built and
parameterised to scale to 64 KB. Supports non-blocking operation through four
miss-status holding registers (MSHRs), allowing hits to proceed while misses are
outstanding, with an LFSR-based pseudo-random replacement policy. Verified in Icarus
Verilog and Questa simulation and synthesised for the DE0-Nano FPGA.
Capacity 1 KB (scales to 64 KB)
Associativity 4-way
Non-blocking MSHR
Replacement LFSR pseudo-random
VerilogCacheMSHRDE0-Nano
Overview
A 20-bit address splits into a 12-bit tag, a 3-bit set index and a 5-bit line offset.
All four tags in a set are compared in parallel, and a write hit merges the byte,
half-word or word into the line and sets its dirty bit. On a miss, a free MSHR records
the request and the victim way; a dirty victim is written back before the fetch, and a
write miss allocates the line. Hits are serviced while a miss is outstanding. The
testbench covers ten scenarios against a 50-cycle memory model; miss-under-miss is only
correct with one miss in flight, a limitation documented in the repository along with
the others found in simulation.
Key Specifications
Data capacity1 KB (8 sets × 4 ways)
Line size32 B (8 words)
CPU interface20-bit address · 32-bit data
Write policyWrite-back · write-allocate
MSHRs4
Replacement16-bit Fibonacci LFSR
Hit latency3 cycles (testbench)
Miss latency57 clean · 111 dirty cycles
Sequential walk87 % hit rate
FPGA targetCyclone IV E (DE0-Nano)
Design Diagrams
20-bit address format8 sets × 4 ways organisationMSHR array (4 entries)MSHR state machineRequest handling decision tree
Homemade PCB Prototyping with CNC & Chemical Etching
Built a home PCB prototyping workflow to enable rapid iteration during competitions
and tight project schedules. This avoided the 1 to 2 week wait for boards from overseas manufacturers.
Bought and modified a small CNC machine for copper milling and explored UV mask + FeCl
etching for finer trace requirements.
Methods CNC milling · UV + FeCl etch
Min trace (milled) 0.4 mm
Min trace (etched) 0.2 mm
Best for Single-layer prototypes
CNC MillingPCB FabricationUV EtchingHardware
Why I Built This
As an undergraduate in Electronic and Telecommunication Engineering, I frequently
needed quick prototypes to test designs before finalising them. Breadboards and
dot boards are unsuitable for SMD packages, complex routing, or sensitive analog circuits
where parasitics from long wires introduce unwanted behaviour. Ordering from JLCPCB or
PCBWay is ideal for final boards, but the 1 to 2 week turnaround and international shipping
cost slowed rapid iteration, which I couldn't afford during competitions and tight
project schedules.
Method 1: CNC Milling
Bought and modified a small CNC machine to accurately mill copper-clad boards. A single
machine handles PCB milling, drilling vias and through-holes, and custom board outlines.
Achieved trace widths down to 0.4 mm. No chemicals involved, fast turnaround, and ideal
for single-layer prototypes. The main limitation is difficulty aligning two-layer boards
and the need for regular bit calibration.
Used a UV-curable photoresist mask and ferric chloride to etch copper traces, achieving
finer detail down to 0.2 mm trace widths. This is better suited to densely packed circuits.
The trade-off is a more time-consuming process, chemical handling and disposal, and
separate steps needed for drilling and board cutting.
Placed 3rd globally in a competition with 1,088 participants from more than 20 countries, including the USA, Germany, UAE, and Iran. I was one of 34 finalists.
Selected as one of 34 finalists out of 1,088 participants across 20 countries to compete in the
20th Annual International Microelectronics Olympiad in Yerevan, Armenia. Competing alongside
top students from the USA, Germany, UAE, and Iran, I won 3rd place and brought
the bronze medal home to Sri Lanka.
Armenia 2025
Receiving the 3rd place awardBronze medalAward ceremonyAward dayFinalists from 20 countriesGala dinner
Champion
IEEE Chips Challenge 2025
2025 · Sri Lanka
Won the national selection round for the International Microelectronics Olympiad by demonstrating strong knowledge in microelectronics and EDA software tools.
Robotics & Embedded Systems
Champions
Dextron 2024: Fast Line Follower
2024 · ITUM, Sri Lanka
Built a differential-drive robot with STM32F411 achieving >0.7 m/s with signal processing for line and pattern detection. First place at a national inter-university robotics event.
Dextron 2024 is an inter-university robotics competition hosted by the NDT Robotic
Club at ITUM. The Fast Line Follower event challenges teams to build the fastest
robot to complete a marked track. The team won championship claiming the Rs. 100,000 prize.
Award
Receiving the Rs. 100,000 champion chequeChampion board, medals & the robot
Run Video
Competition run at Dextron 2024
Champions
UWU Robot Battle 2.0: Death Race
Uva Wellassa University, Sri Lanka
Our team, Raspi Cap, designed and built a 6 kg combat robot with 300 W power, a rotary weapon, and a robotic arm. We won 1st place against 55 teams in a race and cage fight.
UWU Robot Battles 2.0 Death Race combined a high-speed obstacle course race with
a cage fight final where all finalists battled simultaneously until one remained.
Team Raspi Cap claimed the champion trophy and LKR 120,000 prize against 55 teams.
The Robot & Competition
Raspi Cap combat robotRound 1 race startObstacle ramp challengePit repairs between rounds
Champion
Receiving LKR 120,000 champion chequeUWU Robot Battles 2.0 champions trophy
Race & Battle Videos
Race track
Bridge obstacle
The fire
Champions
Robofest 2025: Micromouse
2025
OBO Mouse v4 is an STM32F405-powered open-source micromouse reaching 3 m/s with PID velocity control and quadrature encoder feedback. It claimed 1st place at Robofest 2025. See the full engineering write-up in Projects →
OBO Mouse v4 is a fully open-source 4WD differential drive micromouse developed at
RoboticGen. The robot uses STM32F405 with dual DRV8833 motor drivers, quadrature
encoder feedback, a gyroscope for heading correction, and IR sensors for maze
wall detection. The team won 1st place at Robofest 2025.
Robot & Maze
OBO Mouse v4 on the mazeFully assembled robotCompetition dayBT control interface
Run Videos
Fast run at Robofest 2025
Diagonal run
Test run
1st Runner-Up
Sri Lankan Robotics Challenge 2022/23
2022/23 · University of Moratuwa, Sri Lanka
Mobile robot that picked up boxes, identified colours, and detected arrow directions in an autonomous challenge.
2nd Runner-Up
IESL RoboGames 2023
2023 · Sri Lanka
Vision-based robot that detected, picked up, and placed coloured balls in the correct targets.
School-level
Gold Medal × 2
All-Island Math Quiz Competition, 2016 & 2017
Silver Medal
National Mathematics Olympiad 2018, Category III
1st Runner-Up
All-Island School Robot Competition 2019
Best Hardware
Yarl Geek Challenge Junior 2019 (Season 8), Best Hardware Application
Background
Research Intern at StarLabs, National University of Singapore (NUS)
Dec 2025 to Jun 2026 · Singapore
Handled the electronics design, simulation, and R&D for a smart reaction wheel
controller prototype for satellite Attitude Determination and Control Systems
(ADCS). Simulated control firmware in Simulink before hardware implementation,
then worked on FOC algorithms and BLDC sensor interfacing.
FOCBLDCADCSSatelliteSingapore
Robotics Team Member at RoboticGen (Startup)
Apr 2025 to Jan 2026 · Colombo, SL
Designed a four-wheel drive system capable of reaching 3 m/s, twice the speed
of the previous version, for an open-source micromouse. Created a STM32F405-powered
PCB for motor control and system management, reducing PCB size by over 40%.
Tuned PID control and integrated sensors to improve robot movement.
STM32F405PCB DesignC++PIDRobotics
B.Sc. Engineering (Hons.) in Electronic & Telecommunication Engineering
2023 to 2027
University of Moratuwa, Sri Lanka. Currently in the final year, cumulative GPA 3.71/4.0 up to semester 6.
Final year project: Low-Power Noise-Shaping SAR-ADC in SKY130 CMOS Process for
Energy Constrained Sensing Applications. Coursework: Analog & Digital Electronics,
Signal Processing, Control Systems, Computer Architecture, Communication Systems,
Embedded Systems Programming, Data Structures and Algorithms.
Final Year · GPA 3.71 / 4.0 (up to Sem 6)
VLSIAnalog ElectronicsDSPControl SystemsEmbedded
G.C.E. Advanced Level in Physical Science
A/L 2021 · O/L 2018
J/Hartley College, Jaffna, Sri Lanka. A/L 2021 in Combined Mathematics, Physics,
and Chemistry. Z-score: 2.4978, Island rank 158th.
G.C.E. O/L 2018 with 9As. Served as Senior Prefect.
Z-score 2.4978 · Island Rank 158th
Combined MathematicsPhysicsSenior Prefect
IEEE CAS Society
Webmaster at University of Moratuwa Chapter. Managing digital presence and technical communications for analog/digital IC design events.
Dec 2025 to Present
E-Club (Electronic Club)
Active member contributing to technical and social initiatives. Photographer/videographer for Career Fair, AGM, and departmental events.
Jan 2025 to Present
Yarl IT Hub
Volunteer and coordinator transforming Northern Sri Lanka into an innovation hub. Grew school robotics competition from 25 to 50+ teams.
Jan 2022 to Present
Let's collaborate
I love working on mixed-signal IC design, especially
low-power, high-speed data converters. My work covers schematic design,
custom test benches, simulation, layout, and three tapeout submissions.
If your work intersects with these areas, please get in touch.
Course completion June 2027 · University of Moratuwa
